Logic Gates Explorer
click inputs and watch signals flow through gates
NAND alone can build any circuit 🖖
NAND is functionally complete: NOT, AND, and OR can all be built entirely from NAND combinations, which is why many real chips standardize on a single small gate primitive.
Every gate is a tiny yes/no decision 🖖
A logic gate reads its inputs as HIGH (1) or LOW (0) voltages and outputs a single 1 or 0 by one fixed rule — AND wants both high, OR wants at least one, XOR wants them to differ. The truth table below is the gate's complete definition: list every input combination with its output and there is nothing left to know. Stack enough of these tiny decisions together and you get adders, memory, and eventually a whole processor.
A correct circuit can still flicker 🖖
Signals do not arrive instantly — each gate adds a small propagation delay, and two paths to the same output can have different lengths. When an input changes, the output can momentarily show the wrong value before settling, called a glitch or hazard, even though the truth table is perfectly correct. Watch the timing strip: the output edge lags the input edge by exactly this gate delay, and in multi-gate circuits those delays stack into visible races.
Example problems
- XOR differs - XOR A=1 B=0 -> 1: true when inputs differ
- NAND universal - NAND(1,1) = 0 - NAND inverts AND; it can build every other gate
- half adder 1+1 - Half adder 1+1: Sum=0 Carry=1 - the same carry ripples through every CPU
- mux select - Multiplexer S=1 routes input B to output regardless of A